Methods for forming insulating regions in a semiconductor device, often referred to as oxide regions since an oxide is most commonly used as the insulating material, are well known. These oxide regions are generally employed, for example, to provide electrical, as well as physical, isolation between metal-oxide-semiconductor (MOS) devices and device regions on a semiconductor substrate. A widely used method for providing such isolation typically includes forming regions of localized oxidation of silicon (LOCOS). A conventional LOCOS process essentially involves the growth of a recessed or semi-recessed oxide in unmasked non-active regions, often referred to as field oxide (FOX) regions, of the silicon substrate. The FOX regions are grown thick enough to reduce parasitic capacitance occurring over these regions, but not so thick as to cause step coverage problems.
A trench isolation process, such as shallow trench isolation (STI), may alternatively be used to fabricate insulating regions in a semiconductor device. The trench isolation structure typically comprises a recess formed in the silicon substrate which is refilled with a dielectric material. Such structures are fabricated by first forming a shallow trench (e.g., less than about one micrometer (μm)) in the silicon substrate, usually by a dry anisotropic etching process. The resulting trench is subsequently refilled with a dielectric material such as chemical vapor deposited (CVD) oxide. The trench is then planarized by an oxide etchback process so that the dielectric material remains only in the trench, with an upper surface of the trench being substantially level with an upper surface of the semiconductor device.
In certain applications, it may be desirable to form a thick oxide region (e.g., about 2 μm or more) in an MOS device. For example, in order to reduce parasitic drain capacitance in the MOS device, a recessed LOCOS process may be used, in conjunction with a CVD oxide process and a partial oxide etchback process, to form a thick oxide region under a drain pad of the device. However, this methodology is undesirable in that the recessed LOCOS process often significantly increases the number of defects in the device, thereby degrading device yield and reliability. Defects resulting from the LOCOS process generally limit the practical depth of the LOCOS region to less than about 2 μm. Additionally, the partial oxide etchback process can cause topography problems, thus further degrading device reliability and performance.
Alternatively, a thick oxide region can be formed by using a recessed LOCOS process in conjunction with a multiple-level CVD oxide process and multiple-level metal process. However, as previously explained, the recessed LOCOS process often causes defects which degrade device yield and reliability. Additionally, the multiple-level CVD oxide and metal processes are complicated and suffer from electromigration problems, which can further degrade device reliability and performance.
In either case, the standard methodologies for forming a thick oxide region in an MOS device are expensive and typically involve the introduction of significant defects in the device which undesirably impact device reliability and performance. Furthermore, these conventional methodologies are generally limited to forming an oxide region having a practical depth of about 2 μm or less.
There exists a need, therefore, for improved techniques for forming a thick insulating region in a semiconductor device that does not suffer from one or more of the above-noted deficiencies typically affecting conventional devices. Furthermore, it would be desirable if such a technique was fully compatible with standard integrated circuit (IC) process technology.